PSCI: Migrate SPDs and TSP to the new platform and framework API

The new PSCI frameworks mandates that the platform APIs and the various
frameworks in Trusted Firmware migrate away from MPIDR based core
identification to one based on core index. Deprecated versions of the old
APIs are still present to provide compatibility but their implementations
are not optimal. This patch migrates the various SPDs exisiting within
Trusted Firmware tree and TSP to the new APIs.

Change-Id: Ifc37e7071c5769b5ded21d0b6a071c8c4cab7836

diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index 5b989e3de79ebbfd095b4bd3c6a063a7ebf64a52..4e8da7454fd16dfdb4b531f3cd9a81eec41cfd36 100644 (file)
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -122,8 +122,7 @@ func tsp_entrypoint
         * primary cpu is running at the moment.
         * --------------------------------------------
         */
-       mrs     x0, mpidr_el1
-       bl      platform_set_stack
+       bl      plat_set_my_stack
 
        /* ---------------------------------------------
         * Perform early platform setup & platform
@@ -248,8 +247,7 @@ func tsp_cpu_on_entry
         * enabled.
         * --------------------------------------------
         */
-       mrs     x0, mpidr_el1
-       bl      platform_set_stack
+       bl      plat_set_my_stack
 
        /* --------------------------------------------
         * Enable the MMU with the DCache disabled. It

diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c
index 9abe9baa0de499540853fc6bd63e1c598f819182..139642d094be530c0f3547c7db3ac05cfb21d653 100644 (file)
--- a/bl32/tsp/tsp_interrupt.c
+++ b/bl32/tsp/tsp_interrupt.c
@@ -49,8 +49,7 @@
  ******************************************************************************/
 void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
 
        tsp_stats[linear_id].sync_fiq_count++;
        if (type == TSP_HANDLE_FIQ_AND_RETURN)
@@ -59,9 +58,9 @@ void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3)
 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
        spin_lock(&console_lock);
        VERBOSE("TSP: cpu 0x%lx sync fiq request from 0x%lx\n",
-               mpidr, elr_el3);
+               read_mpidr(), elr_el3);
        VERBOSE("TSP: cpu 0x%lx: %d sync fiq requests, %d sync fiq returns\n",
-               mpidr,
+               read_mpidr(),
                tsp_stats[linear_id].sync_fiq_count,
                tsp_stats[linear_id].sync_fiq_ret_count);
        spin_unlock(&console_lock);
@@ -77,8 +76,7 @@ void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3)
  ******************************************************************************/
 int32_t tsp_fiq_handler(void)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr), id;
+       uint32_t linear_id = plat_my_core_pos(), id;
 
        /*
         * Get the highest priority pending interrupt id and see if it is the
@@ -105,9 +103,9 @@ int32_t tsp_fiq_handler(void)
 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
        spin_lock(&console_lock);
        VERBOSE("TSP: cpu 0x%lx handled fiq %d\n",
-              mpidr, id);
+              read_mpidr(), id);
        VERBOSE("TSP: cpu 0x%lx: %d fiq requests\n",
-            mpidr, tsp_stats[linear_id].fiq_count);
+            read_mpidr(), tsp_stats[linear_id].fiq_count);
        spin_unlock(&console_lock);
 #endif
        return 0;
@@ -115,15 +113,14 @@ int32_t tsp_fiq_handler(void)
 
 int32_t tsp_irq_received(void)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
 
        tsp_stats[linear_id].irq_count++;
 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
        spin_lock(&console_lock);
-       VERBOSE("TSP: cpu 0x%lx received irq\n", mpidr);
+       VERBOSE("TSP: cpu 0x%lx received irq\n", read_mpidr());
        VERBOSE("TSP: cpu 0x%lx: %d irq requests\n",
-               mpidr, tsp_stats[linear_id].irq_count);
+               read_mpidr(), tsp_stats[linear_id].irq_count);
        spin_unlock(&console_lock);
 #endif
        return TSP_PREEMPTED;

diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index 2a4ce4f9d493883cc3b89565c0b80ca24883a67a..b002addfba98c9490e15f622914f60c32e9fdc34 100644 (file)
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -72,7 +72,6 @@ static tsp_args_t *set_smc_args(uint64_t arg0,
                             uint64_t arg6,
                             uint64_t arg7)
 {
-       uint64_t mpidr = read_mpidr();
        uint32_t linear_id;
        tsp_args_t *pcpu_smc_args;
 
@@ -80,7 +79,7 @@ static tsp_args_t *set_smc_args(uint64_t arg0,
         * Return to Secure Monitor by raising an SMC. The results of the
         * service are passed as an arguments to the SMC
         */
-       linear_id = platform_get_core_pos(mpidr);
+       linear_id = plat_my_core_pos();
        pcpu_smc_args = &tsp_smc_args[linear_id];
        write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0);
        write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1);
@@ -107,8 +106,7 @@ uint64_t tsp_main(void)
        INFO("TSP: Total memory size : 0x%lx bytes\n",
                         BL32_TOTAL_LIMIT - BL32_TOTAL_BASE);
 
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
 
        /* Initialize the platform */
        tsp_platform_setup();
@@ -123,7 +121,8 @@ uint64_t tsp_main(void)
 
 #if LOG_LEVEL >= LOG_LEVEL_INFO
        spin_lock(&console_lock);
-       INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", mpidr,
+       INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
+            read_mpidr(),
             tsp_stats[linear_id].smc_count,
             tsp_stats[linear_id].eret_count,
             tsp_stats[linear_id].cpu_on_count);
@@ -139,8 +138,7 @@ uint64_t tsp_main(void)
  ******************************************************************************/
 tsp_args_t *tsp_cpu_on_main(void)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
 
        /* Initialize secure/applications state here */
        tsp_generic_timer_start();
@@ -152,8 +150,9 @@ tsp_args_t *tsp_cpu_on_main(void)
 
 #if LOG_LEVEL >= LOG_LEVEL_INFO
        spin_lock(&console_lock);
-       INFO("TSP: cpu 0x%lx turned on\n", mpidr);
-       INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", mpidr,
+       INFO("TSP: cpu 0x%lx turned on\n", read_mpidr());
+       INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
+               read_mpidr(),
                tsp_stats[linear_id].smc_count,
                tsp_stats[linear_id].eret_count,
                tsp_stats[linear_id].cpu_on_count);
@@ -176,8 +175,7 @@ tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
                           uint64_t arg6,
                           uint64_t arg7)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
 
        /*
         * This cpu is being turned off, so disable the timer to prevent the
@@ -193,8 +191,9 @@ tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
 
 #if LOG_LEVEL >= LOG_LEVEL_INFO
        spin_lock(&console_lock);
-       INFO("TSP: cpu 0x%lx off request\n", mpidr);
-       INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", mpidr,
+       INFO("TSP: cpu 0x%lx off request\n", read_mpidr());
+       INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
+               read_mpidr(),
                tsp_stats[linear_id].smc_count,
                tsp_stats[linear_id].eret_count,
                tsp_stats[linear_id].cpu_off_count);
@@ -219,8 +218,7 @@ tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
                               uint64_t arg6,
                               uint64_t arg7)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
 
        /*
         * Save the time context and disable it to prevent the secure timer
@@ -237,7 +235,7 @@ tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
 #if LOG_LEVEL >= LOG_LEVEL_INFO
        spin_lock(&console_lock);
        INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
-               mpidr,
+               read_mpidr(),
                tsp_stats[linear_id].smc_count,
                tsp_stats[linear_id].eret_count,
                tsp_stats[linear_id].cpu_suspend_count);
@@ -262,8 +260,7 @@ tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level,
                              uint64_t arg6,
                              uint64_t arg7)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
 
        /* Restore the generic timer context */
        tsp_generic_timer_restore();
@@ -276,9 +273,9 @@ tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level,
 #if LOG_LEVEL >= LOG_LEVEL_INFO
        spin_lock(&console_lock);
        INFO("TSP: cpu 0x%lx resumed. suspend level %ld\n",
-               mpidr, suspend_level);
+               read_mpidr(), suspend_level);
        INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
-               mpidr,
+               read_mpidr(),
                tsp_stats[linear_id].smc_count,
                tsp_stats[linear_id].eret_count,
                tsp_stats[linear_id].cpu_suspend_count);
@@ -301,8 +298,7 @@ tsp_args_t *tsp_system_off_main(uint64_t arg0,
                                uint64_t arg6,
                                uint64_t arg7)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
 
        /* Update this cpu's statistics */
        tsp_stats[linear_id].smc_count++;
@@ -310,8 +306,8 @@ tsp_args_t *tsp_system_off_main(uint64_t arg0,
 
 #if LOG_LEVEL >= LOG_LEVEL_INFO
        spin_lock(&console_lock);
-       INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", mpidr);
-       INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", mpidr,
+       INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr());
+       INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
             tsp_stats[linear_id].smc_count,
             tsp_stats[linear_id].eret_count);
        spin_unlock(&console_lock);
@@ -334,8 +330,7 @@ tsp_args_t *tsp_system_reset_main(uint64_t arg0,
                                uint64_t arg6,
                                uint64_t arg7)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
 
        /* Update this cpu's statistics */
        tsp_stats[linear_id].smc_count++;
@@ -343,8 +338,8 @@ tsp_args_t *tsp_system_reset_main(uint64_t arg0,
 
 #if LOG_LEVEL >= LOG_LEVEL_INFO
        spin_lock(&console_lock);
-       INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", mpidr);
-       INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", mpidr,
+       INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr());
+       INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
             tsp_stats[linear_id].smc_count,
             tsp_stats[linear_id].eret_count);
        spin_unlock(&console_lock);
@@ -371,17 +366,16 @@ tsp_args_t *tsp_smc_handler(uint64_t func,
 {
        uint64_t results[2];
        uint64_t service_args[2];
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
 
        /* Update this cpu's statistics */
        tsp_stats[linear_id].smc_count++;
        tsp_stats[linear_id].eret_count++;
 
-       INFO("TSP: cpu 0x%lx received %s smc 0x%lx\n", mpidr,
+       INFO("TSP: cpu 0x%lx received %s smc 0x%lx\n", read_mpidr(),
                ((func >> 31) & 1) == 1 ? "fast" : "standard",
                func);
-       INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", mpidr,
+       INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),
                tsp_stats[linear_id].smc_count,
                tsp_stats[linear_id].eret_count);
 

diff --git a/bl32/tsp/tsp_timer.c b/bl32/tsp/tsp_timer.c
index f196021d0794f80684169243a438ca6bc072b01c..7ca87340184795da125212608bfecc9cb71e3032 100644 (file)
--- a/bl32/tsp/tsp_timer.c
+++ b/bl32/tsp/tsp_timer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -92,7 +92,7 @@ void tsp_generic_timer_stop(void)
  ******************************************************************************/
 void tsp_generic_timer_save(void)
 {
-       uint32_t linear_id = platform_get_core_pos(read_mpidr());
+       uint32_t linear_id = plat_my_core_pos();
 
        pcpu_timer_context[linear_id].cval = read_cntps_cval_el1();
        pcpu_timer_context[linear_id].ctl = read_cntps_ctl_el1();
@@ -105,7 +105,7 @@ void tsp_generic_timer_save(void)
  ******************************************************************************/
 void tsp_generic_timer_restore(void)
 {
-       uint32_t linear_id = platform_get_core_pos(read_mpidr());
+       uint32_t linear_id = plat_my_core_pos();
 
        write_cntps_cval_el1(pcpu_timer_context[linear_id].cval);
        write_cntps_ctl_el1(pcpu_timer_context[linear_id].ctl);

diff --git a/services/spd/opteed/opteed_main.c b/services/spd/opteed/opteed_main.c
index 5c5144fb94babc97dc634b192d483fa0666a7873..fefc8a75e8f8ecb08ef02b94564c6f1679f042e2 100644 (file)
--- a/services/spd/opteed/opteed_main.c
+++ b/services/spd/opteed/opteed_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -80,7 +80,6 @@ static uint64_t opteed_sel1_interrupt_handler(uint32_t id,
                                            void *cookie)
 {
        uint32_t linear_id;
-       uint64_t mpidr;
        optee_context_t *optee_ctx;
 
        /* Check the security state when the exception was generated */
@@ -92,14 +91,13 @@ static uint64_t opteed_sel1_interrupt_handler(uint32_t id,
 #endif
 
        /* Sanity check the pointer to this cpu's context */
-       mpidr = read_mpidr();
        assert(handle == cm_get_context(NON_SECURE));
 
        /* Save the non-secure context before entering the OPTEE */
        cm_el1_sysregs_context_save(NON_SECURE);
 
        /* Get a reference to this cpu's OPTEE context */
-       linear_id = platform_get_core_pos(mpidr);
+       linear_id = plat_my_core_pos();
        optee_ctx = &opteed_sp_context[linear_id];
        assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE));
 
@@ -125,10 +123,9 @@ static uint64_t opteed_sel1_interrupt_handler(uint32_t id,
 int32_t opteed_setup(void)
 {
        entry_point_info_t *optee_ep_info;
-       uint64_t mpidr = read_mpidr();
        uint32_t linear_id;
 
-       linear_id = platform_get_core_pos(mpidr);
+       linear_id = plat_my_core_pos();
 
        /*
         * Get information about the Secure Payload (BL32) image. Its
@@ -182,8 +179,7 @@ int32_t opteed_setup(void)
  ******************************************************************************/
 static int32_t opteed_init(void)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
        entry_point_info_t *optee_entry_point;
        uint64_t rc;
@@ -195,7 +191,7 @@ static int32_t opteed_init(void)
        optee_entry_point = bl31_plat_get_next_image_ep_info(SECURE);
        assert(optee_entry_point);
 
-       cm_init_context(mpidr, optee_entry_point);
+       cm_init_my_context(optee_entry_point);
 
        /*
         * Arrange for an entry into OPTEE. It will be returned via
@@ -226,8 +222,7 @@ uint64_t opteed_smc_handler(uint32_t smc_fid,
                         uint64_t flags)
 {
        cpu_context_t *ns_cpu_context;
-       unsigned long mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
        uint64_t rc;
 

diff --git a/services/spd/opteed/opteed_pm.c b/services/spd/opteed/opteed_pm.c
index 37419ec77c35ebc208138be8c8b2f83ed4e2eb4f..50994d0112257028bacd29446227bf60cca0155d 100644 (file)
--- a/services/spd/opteed/opteed_pm.c
+++ b/services/spd/opteed/opteed_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -51,8 +51,7 @@ static void opteed_cpu_on_handler(uint64_t target_cpu)
 static int32_t opteed_cpu_off_handler(uint64_t unused)
 {
        int32_t rc = 0;
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
 
        assert(optee_vectors);
@@ -85,8 +84,7 @@ static int32_t opteed_cpu_off_handler(uint64_t unused)
 static void opteed_cpu_suspend_handler(uint64_t unused)
 {
        int32_t rc = 0;
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
 
        assert(optee_vectors);
@@ -116,8 +114,7 @@ static void opteed_cpu_suspend_handler(uint64_t unused)
 static void opteed_cpu_on_finish_handler(uint64_t unused)
 {
        int32_t rc = 0;
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
        entry_point_info_t optee_on_entrypoint;
 
@@ -129,7 +126,7 @@ static void opteed_cpu_on_finish_handler(uint64_t unused)
                                optee_ctx);
 
        /* Initialise this cpu's secure context */
-       cm_init_context(mpidr, &optee_on_entrypoint);
+       cm_init_my_context(&optee_on_entrypoint);
 
        /* Enter OPTEE */
        rc = opteed_synchronous_sp_entry(optee_ctx);
@@ -153,8 +150,7 @@ static void opteed_cpu_on_finish_handler(uint64_t unused)
 static void opteed_cpu_suspend_finish_handler(uint64_t suspend_level)
 {
        int32_t rc = 0;
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
 
        assert(optee_vectors);
@@ -193,8 +189,7 @@ static int32_t opteed_cpu_migrate_info(uint64_t *resident_cpu)
  ******************************************************************************/
 static void opteed_system_off(void)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
 
        assert(optee_vectors);
@@ -214,8 +209,7 @@ static void opteed_system_off(void)
  ******************************************************************************/
 static void opteed_system_reset(void)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
 
        assert(optee_vectors);

diff --git a/services/spd/tlkd/tlkd_main.c b/services/spd/tlkd/tlkd_main.c
index 3532bebe58b6dafa9f494548e86e5f972284d4ad..58a60464d6ab477cac991a51fc004014b7083697 100644 (file)
--- a/services/spd/tlkd/tlkd_main.c
+++ b/services/spd/tlkd/tlkd_main.c
@@ -121,7 +121,6 @@ int32_t tlkd_setup(void)
  ******************************************************************************/
 int32_t tlkd_init(void)
 {
-       uint64_t mpidr = read_mpidr();
        entry_point_info_t *tlk_entry_point;
 
        /*
@@ -131,7 +130,7 @@ int32_t tlkd_init(void)
        tlk_entry_point = bl31_plat_get_next_image_ep_info(SECURE);
        assert(tlk_entry_point);
 
-       cm_init_context(mpidr, tlk_entry_point);
+       cm_init_my_context(tlk_entry_point);
 
        /*
         * Arrange for an entry into the test secure payload.

diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c
index ee17483e1d5020830b75cbc5bb7865905d79a48c..b8b67fadc85636b00b2fb336faddffb1d458ea1d 100644 (file)
--- a/services/spd/tspd/tspd_main.c
+++ b/services/spd/tspd/tspd_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -101,7 +101,6 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
                                            void *cookie)
 {
        uint32_t linear_id;
-       uint64_t mpidr;
        tsp_context_t *tsp_ctx;
 
        /* Check the security state when the exception was generated */
@@ -113,14 +112,13 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
 #endif
 
        /* Sanity check the pointer to this cpu's context */
-       mpidr = read_mpidr();
        assert(handle == cm_get_context(NON_SECURE));
 
        /* Save the non-secure context before entering the TSP */
        cm_el1_sysregs_context_save(NON_SECURE);
 
        /* Get a reference to this cpu's TSP context */
-       linear_id = platform_get_core_pos(mpidr);
+       linear_id = plat_my_core_pos();
        tsp_ctx = &tspd_sp_context[linear_id];
        assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE));
 
@@ -197,10 +195,9 @@ static uint64_t tspd_ns_interrupt_handler(uint32_t id,
 int32_t tspd_setup(void)
 {
        entry_point_info_t *tsp_ep_info;
-       uint64_t mpidr = read_mpidr();
        uint32_t linear_id;
 
-       linear_id = platform_get_core_pos(mpidr);
+       linear_id = plat_my_core_pos();
 
        /*
         * Get information about the Secure Payload (BL32) image. Its
@@ -256,8 +253,7 @@ int32_t tspd_setup(void)
  ******************************************************************************/
 int32_t tspd_init(void)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
        entry_point_info_t *tsp_entry_point;
        uint64_t rc;
@@ -269,7 +265,7 @@ int32_t tspd_init(void)
        tsp_entry_point = bl31_plat_get_next_image_ep_info(SECURE);
        assert(tsp_entry_point);
 
-       cm_init_context(mpidr, tsp_entry_point);
+       cm_init_my_context(tsp_entry_point);
 
        /*
         * Arrange for an entry into the test secure payload. It will be
@@ -300,8 +296,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
                         uint64_t flags)
 {
        cpu_context_t *ns_cpu_context;
-       unsigned long mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr), ns;
+       uint32_t linear_id = plat_my_core_pos(), ns;
        tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
        uint64_t rc;
 #if TSP_INIT_ASYNC
@@ -453,7 +448,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
 
                        /*
                         * Disable the interrupt NS locally since it will be enabled globally
-                        * within cm_init_context.
+                        * within cm_init_my_context.
                         */
                        disable_intr_rm_local(INTR_TYPE_NS, SECURE);
 #endif
@@ -471,7 +466,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
                assert(NON_SECURE ==
                                GET_SECURITY_STATE(next_image_info->h.attr));
 
-               cm_init_context(read_mpidr_el1(), next_image_info);
+               cm_init_my_context(next_image_info);
                cm_prepare_el3_exit(NON_SECURE);
                SMC_RET0(cm_get_context(NON_SECURE));
 #else

diff --git a/services/spd/tspd/tspd_pm.c b/services/spd/tspd/tspd_pm.c
index 009ff5f4d23136ed4d1b1d084e4699e06e7dd86c..bc9eb76593edac1822a854c56e5355762a548908 100644 (file)
--- a/services/spd/tspd/tspd_pm.c
+++ b/services/spd/tspd/tspd_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -52,8 +52,7 @@ static void tspd_cpu_on_handler(uint64_t target_cpu)
 static int32_t tspd_cpu_off_handler(uint64_t unused)
 {
        int32_t rc = 0;
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
 
        assert(tsp_vectors);
@@ -86,8 +85,7 @@ static int32_t tspd_cpu_off_handler(uint64_t unused)
 static void tspd_cpu_suspend_handler(uint64_t unused)
 {
        int32_t rc = 0;
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
 
        assert(tsp_vectors);
@@ -117,8 +115,7 @@ static void tspd_cpu_suspend_handler(uint64_t unused)
 static void tspd_cpu_on_finish_handler(uint64_t unused)
 {
        int32_t rc = 0;
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
        entry_point_info_t tsp_on_entrypoint;
 
@@ -131,12 +128,12 @@ static void tspd_cpu_on_finish_handler(uint64_t unused)
                                tsp_ctx);
 
        /* Initialise this cpu's secure context */
-       cm_init_context(mpidr, &tsp_on_entrypoint);
+       cm_init_my_context(&tsp_on_entrypoint);
 
 #if TSPD_ROUTE_IRQ_TO_EL3
        /*
         * Disable the NS interrupt locally since it will be enabled globally
-        * within cm_init_context.
+        * within cm_init_my_context.
         */
        disable_intr_rm_local(INTR_TYPE_NS, SECURE);
 #endif
@@ -163,8 +160,7 @@ static void tspd_cpu_on_finish_handler(uint64_t unused)
 static void tspd_cpu_suspend_finish_handler(uint64_t suspend_level)
 {
        int32_t rc = 0;
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
 
        assert(tsp_vectors);
@@ -203,8 +199,7 @@ static int32_t tspd_cpu_migrate_info(uint64_t *resident_cpu)
  ******************************************************************************/
 static void tspd_system_off(void)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
 
        assert(tsp_vectors);
@@ -224,8 +219,7 @@ static void tspd_system_off(void)
  ******************************************************************************/
 static void tspd_system_reset(void)
 {
-       uint64_t mpidr = read_mpidr();
-       uint32_t linear_id = platform_get_core_pos(mpidr);
+       uint32_t linear_id = plat_my_core_pos();
        tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
 
        assert(tsp_vectors);